1. Field of the Invention
The present invention generally relates to digital input/output circuits and more specifically to a level shifter circuit to shift signals from a logic voltage to an input/output voltage.
2. Description of the Related Art
Conventional integrated circuit devices use different voltage levels for input/output (I/O) circuitry and logic circuitry. The I/O circuitry interfaces with other devices in a system and typically uses a higher voltage, e.g., 3.3 or 2.5 volts, compared with the logic circuitry. As the logic circuitry scales down in size to use the newer silicon technologies, the voltage level used for the logic circuitry is reduced. For example a 90 nanometer silicon process may use a 1.2 volt supply and a 65 nanometer silicon process may use a 1 volt supply. As the difference in voltage levels between the I/O circuitry and logic circuitry increases, the difficulty of shifting the voltage level of signals from the logic domain to the I/O domain is increased.
FIG. 1 illustrates a level shifter circuit 100 configured to shift signals from a VDD_Logic voltage level to a VDD_IO voltage level, according to the prior art. Circuit 100 includes two PMOS transistors, 115 and 135 and two NMOS transistors, 110 and 130. Transistors 115, 110, 135, and 130 are all designed to operate at VDD_IO, i.e., are input/output devices. Inverter 132 is also designed to operate at VDD_IO. Inverters 122 and 127 are designed to operate at VDD_Logic, i.e., are logic devices, so that the gate oxide is reliable up to a maximum voltage across the gate and source (gate to source voltage or Vgs) of approximately VDD_Logic*1.2.
VDD 125 is set to VDD_IO and ground 220 is set to the ground voltage of 0 volts. The input 105 ranges between ground and VDD_Logic and the output 150 should range between ground and VDD_IO. When a VDD_Logic of 1.2 volts is applied to input 105, the output of inverter 122 is discharged to ground and the output of inverter 127 is pulled up to VDD_Logic. Transistors 115 and 130 are activated and the input to inverter 132 is discharged to ground while output 150 is pulled up to VDD_IO (assuming VDD_Logic is greater than the threshold voltage, Vth of the input/output devices).
When input 105 transitions to ground, the output of inverter 122 is pulled up to VDD_Logic and the output of inverter 127 is discharged to ground. Transistors 135 and 110 are activated and the input to inverter 132 is pulled up to VDD_IO while output 150 is discharged to ground (assuming VDD_Logic is greater than the threshold voltage, Vth_IO of the input/output devices).
However, when a silicon process is used that allows the size of logic circuitry to be reduced to use a VDD_Logic of 0.9 volts, such as a 45 nanometer process, circuit 100 may not function properly. Also, when circuit 100 is configured to use a VDD_logic of 0.8 volts for a low power application, the circuit 100 may not function properly. When VDD_logic is equal or less than Vth_IO, transistors 110 and 130 to be only weakly activated or not activated and unable to discharge the gate of transistor 135 or 115, respectively. As a result, the input of inverter 132 may not be discharged to drive output 150 to VDD_IO, causing the output 150 to be unknown.
Replacing transistors 110 and 130 with transistors configured to operate at logic levels solves the VDD_Logic scaling down problem. However, a gate oxide reliability problem is created. Assuming a VDD_Logic of 1.0 volts, the maximum tolerable Vgs (or Vds) of the logic transistor is VDD_logic*1.2=1.2 volts. When input 105 is at VDD_Logic, the output of inverter 122 is discharged to ground and the gate of transistor 135 is at VDD_IO. The Vgs of the logic transistor (replacing input/output transistor 110) is VDD_IO. When VDD_IO exceeds the maximum tolerable Vgs of 1.2 volts, the gate oxide of the logic transistor is compromised and breaks down over time, impairing proper operation of the circuit.
A voltage reference may be used to avoid the gate oxide reliability problem and the VDD_Logic scaling problem. FIG. 2 illustrates a level shifter circuit 200, configured to shift signals from a VDD_Logic voltage level to a VDD_IO voltage level using a voltage reference, according to the prior art. Circuit 200 includes two PMOS transistors, 215 and 235 and four NMOS transistors, 240, 245, 210, and 230. Transistors 215, 235, 240, and 245 and inverter 232 are input/output devices that are designed to operate at VDD_IO. Transistors 210 and 230 and inverters 222 and 227 are logic devices that are designed to operate at VDD_Logic. VDD_IO 225 is set to VDD_IO and ground 220 is set to the ground voltage of 0 volts. Input 205 ranges between ground and VDD_Logic and output 250 should range between ground and VDD_IO.
Circuit 200 also includes a voltage reference, Vref 207 that equals VDD_IO*R2/(R1+R2), where R2 is the resistance of 202 and R1 is the resistance of 201. When input 205 is at VDD_Logic, the output of inverter 222 is at ground. Assuming that the maximum allowable Vgs at node 242 is Vc_max, the maximum Vref=Vc_max+Vth_IO, where Vth_IO is the threshold voltage of an input/output transistor. In order to activate input/output transistors 240 and 245, and maintain adequate overdrive (Vgs−Vth), the minimum Vref=Vth_IO+0.3 volts. Therefore, Vc_max should be greater than VDD_IO*R2/(R1+R2)−Vth_IO. The values of R1 and R2 are determined for each different VDD_IO. For example, when VDD_IO is 3.3 volts, VDD_Logic is 1.0 volts, Vth_IO is 0.9 volts, Vc_max is 1.2 volts, R1 equals R2, and Vref is 1.65 volts. The voltage at node 242 is 1.65−0.9=0.75 volts. If VDD_IO is changed t 1.8 volts, Vref is 0.9 volts and transistors 240 and 245 cannot be activated.
Accordingly, what is needed in the art is a system and method for shifting the voltage level of signals from the logic domain to the I/O domain that is independent of VDD_IO and operates as the logic circuitry size changes.